Low-Voltage Differential Signaling (LVDS) is an interface standard that can be used for high-speed data transmission. By using low swing signals (typically about 300 mV), fast bit rates, lower power, and better noise performance can be achieved. The differential nature allows for increased noise immunity and noise margins. Examples of applications that use LVDS signaling include hubs for data communications, base stations and switches for telecommunications, flat-panel displays and servers, peripheral devices including printers and digital copy machines, and high-resolution displays for industrial applications.
Most integrated circuit (IC) or “chip” driver circuits designed to implement an LVDS interface include circuits that use a 2.5V or higher power supply. A typical conventional driver circuit design is shown in FIG. 1. The circuit includes two operational amplifiers (amp1 and amp2) to generate internal vdd_voh and vss_vol power supplies, respectively. The p-type metal oxide semiconductor (PMOS) (i.e., p-channel) and n-type metal oxide semiconductor (NMOS) (i.e., n-channel) transistors referenced to these supplies can be designed to produce the desired signal swing and common mode voltage. These switching transistors connected to vdd_voh and vss_vol require full rail (about 2.5V in this example) complementary metal oxide semiconductor (CMOS) signal levels at their gates to fully switch the output transistors (e.g., Q5, Q6, Q7 and Q8). The skew between input true and complement signals are very low to achieve the signal integrity specified in the LVDS standard. For clarity, the low voltage to high voltage level translators as well as additional conventional circuitry to minimize the skew are not shown in FIG. 1.
Disadvantages of the above approach include a lack of functionality at lower power supplies, such as about 1.8V or lower, using transistors with a 2.5V compatible process. According to one LVDS standard, the nominal output common mode voltage is about 1.25 volts. This further requires a sufficient drive on the NMOS output transistors (Q6 and Q8) to accommodate the Vol (maximum output voltage for “low” signal detection) specification. In the above design, the NMOS output transistors (Q6 and Q8), for example, will not sufficiently turn on at such low voltage to provide the appropriate output levels and signal integrity over process/voltage/temperature (PVT) corners with a power supply at or below approximately 1.8V.